Clock frequencies used in large-scale integrated circuits (LSI circuits) have reached the gigahertz band in recent years. In an LSI circuit, clock signal is distributed to all clock synchronous elements via a clock distribution network (wirings and buffer circuits, etc.). Tree-type and grid-type clock distribution arrangements have long been used as typical means for clock distribution adapted to reduce a phase difference at the clock terminals of the clock-synchronous elements within an LSI circuit.
With the tree (H-tree) arrangement, the clock branches in the form of a tree and is supplied to the clock synchronous elements (load circuits) from a centrally located clock driver, and repeaters (buffers) are placed at the signal branch points (see FIG. 6A). In the H-tree distribution system, the distances from the clock driver to load circuits at the ends of the branches are equal if the system is well-balanced.
On the other hand, an interconnection structure in which the clock supply lines extend in the directions of rows and columns and load circuits are placed at grid points is in use as a grid-type arrangement (see FIG. 6B).
Also known is an arrangement such as a tree-driven grid that is a mixture of the tree- and grid-type arrangements. With regard to a configuration in which both the H-tree and grid arrangements are combined as a global clock distribution system in which a clock is distributed to all synchronized elements in an LSI circuit, see the descriptions given in Non-Patent Documents 1 and 2, etc.
In cases where the tree system is used for global clock distribution, a buffer (repeater) is placed at each terminal point of the tree and at each branch point where the wiring branches in two directions. In order to distribute a gigahertz-band clock within an LSI chip while suppressing clock skew throughout the interior of the chip, it is required that the delay times of the repeaters in the terminal stages be adjusted in ps units, by way of example. Consequently, in a case where an ultra-high-speed clock is distributed in large scale and multiple layers in an LSI chip, the delay times of the repeaters in the terminal stages constitute an obstacle and implementation is difficult. In addition, in order to equalize load with the tree arrangement, a balanced branching configuration is required. However, achieving perfect balance is difficult.
Further, with the tree-type clock distribution, jitter can be kept small in a case where the hierarchical level (number of stages) of a branch is shallow. When the level of a layer increases, however, so does jitter. In the case of the tree-type global clock distribution, the scale of signal distribution depends upon the characteristics and performance (e.g., jigger, delay, variation and power dissipation) of the repeaters, as mentioned above. Application of this technique to LSI circuits that will be of even larger scale and higher speed in the future will be difficult.
Thus, large-scale clock distribution in a microprocessor operated at a clock frequency of gigahertz band has become increasingly difficult. Skew and jitter are proportional to latency. With the conventional tree architecture, however, a reduction in latency does not go hand in hand with a shortening of clock period.
With tree- or grid-type clock distribution, the clock is propagated using traveling waves (not standing waves) and the range of clock-skew adjustment is 10 ps at most.
Holding the amount of skew or jitter to less than 5% of the clock period is accepted as one criteria, and 5 GHz is assumed to be the upper limit in the case of the H-tree.
In order to produce and distribute a clock having a frequency greater than the 10 GHz that is necessary for ultra-high-speed logic, a clock distribution system that relies upon standing waves, which do not include traveling waves, instead of non-standing waves, has been proposed (e.g., see Non-Patent Document 3 or Non-Patent Document 4).
In the case of the topology proposed in Non-Patent Document 3, a tank circuit is formed at each tree branch point and inductors placed in the branches are adjusted individually to mitigate skew, as illustrated in FIGS. 7A and 7B. Patent Document 1 also discloses an arrangement of the kind illustrated in FIGS. 7A and 7B. In the case of FIGS. 7A and 7B, however, the adjusting locations are of a scale equivalent to that for adjusting delay time in a system that uses repeaters, such as the tree-type system. Accordingly, this arrangement is not suited to clock distribution in very large LSI circuits.
Further, Non-Patent Document 4 discloses an arrangement in which the frequency of standing waves in signal wiring is made to coincide with clock frequency to reduce clock skew of the entire chip at physical placement positions and make possible distribution of an ultra-high-frequency clock of 10 GHz, etc., using a 0.18 μm standard CMOS process, as illustrated in FIGS. 8A and 8B. A standing-wave oscillator (SWO) eliminates wire losses using distributed gain and maintains low-skew standing waves. NMOS cross-coupled pairs provide enough gain to compensate for wire losses. The ends of differential transmission line are short-circuited to produce a half-wave length resonator.
In the arrangement of FIGS. 8A and 8B, however, the amplitude of the standing waves varies with location. Further, the length of transmission lines is fixed at λ/2 and the system does not adapt itself well to physical changes such as scaling.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-159353A
[Non-Patent Document 1]
P. Hofstee, N. Aoki, D. Boerstler, P. Coulman, S. Dhong, B. Flachs, N. Kojima, O. Kwon, K. Lee, D. Meltzer, K. Nowka, J. Park, J. Peter, S. Posluszny, M. Shapiro, J. Silberman, O. Takahashi, B. Weinberger, “A 1 GHz Single-Issue 64b PowerPC Processor,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2000
[Non-Patent Document 2]
T. McPherson, R. Averill, D. Balazich, K. Barkley, S. Carey, Y. Chan, Y. H. Chan, R. Crea, A. Dansky, R. Dwyer, A. Haen, D. Hoffman, A. Jatkowski, M. Mayo, D. Merrill, T. McNamara, G. Northrop, J. Rawlins, L. Sigal, T. Slegel, D. Webber, P. Willimans, F. Yee, “760 MHz G6 S/390 Microprocessor Exploiting Multiple Vt and Copper Interconnects,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2000
[Non-Patent Document 3]
Steven C. Chan, Kenneth L. Shepard and Phillip J. Restle, “Uniform-Phase Uniform-Amplitude Resonant-Load Global Clock Distributions,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, January 2005
[Non-Patent Document 4]
Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong, 24-4, “10 GHz Clock Distribution Using Coupled Standing-Wave Oscillators,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 428-429, 2003
[Non-Patent Document 5]
Niraj Bindal, Timothy Kelly, Nicholas Velastegui, Keng L. Wong, “Scalable Sub-10 ps Skew Global Clock Distribution for a 90 nm Multi-GHz IA Microprocessor,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 346-347 February 2003